The present invention relates generally to the field of ingrated circuits, and more particularly to a method of fabricating a transistor device having a generally T-shaped gate.
MOS type transistors are a fundamental building block within integrated circuits. Consequently, there is a persistent push to make such devices smaller, faster, etc. The switching speed of a transistor is an important characteristic since it dictates, at least in one respect, how fast the circuits which employ such devices operate. Presently, the switching speed of a transistor is not always limited by the channel transit time (i.e., the time required for charge to be transported across the channel); instead, the switching speed sometimes is limited by the time required to charge and discharge the capacitances that exist between the device electrodes and between the interconnecting conductive lines and the substrate.
One way of appreciating the transistor capacitances is through an exemplary cross section, as illustrated in prior art FIG. 1. The transistor, an NMOS transistor designated at reference numeral 10, includes a p-type region 12 (sometimes referred to as the body), such as a P-well or substrate in a CMOS type process. The body 12 has an n-type drain region 14 and a source region 18 formed therein. A doped polysilicon gate 22 overlies a thin gate oxide 24 which defines a channel region 26 therebeneath in the body 12.
An effective circuit diagram illustrating the various capacitances associated with the transistor 10 is illustrated in prior art FIG. 2 and designated at reference numeral 30. As seen in prior art FIG. 2, capacitances exist between the various device electrodes and between the electrodes and the body region. The drain-to-body capacitance (Cdb) and the source-to-body capacitance (Csb) are illustrated in prior art FIG. 2 and are referred to often as junction capacitances. The value of the junction capacitances are a function of both the cross sectional area of the junctions as well as the doping concentrations of the regions, respectively. Similarly, the gate-to-drain capacitance (Cgd) and the gate-to-source capacitance (Cgs) illustrated in FIG. 2 are often collectively referred to as a gate overlap capacitance. The value of such capacitances are a function of the gate oxide thickness and the degree of overlap between the gate and source/drain regions, respectively.
Several developments have occurred which are directed to the reduction in the gate-to-drain (Cgd) and the gate-to-source (Cgs) capacitances in order to increase device speed. For example, as illustrated in prior art FIG. 3a, after the gate region 22 is defined, an implantation step occurs, by which dopants 40 are implanted into the substrate 12. Since the implantation of dopants (e.g., n-type dopants for an NMOS transistor) cause lattice damage, a subsequent thermal processing step (sometimes referred to as an anneal) is conducted. The thermal processing causes the dopants 40 to diffuse and the lattice to be repaired, thereby causing the drain and source regions 14 and 18, respectively, to extend substantially under lateral portions 42 of the gate electrode 22, as illustrated in prior art FIG. 3b. The extent or distance (e.g., Dgd illustrated in prior art FIG. 3c) in which the source and drain regions diffuse under the gate contributes to Cgd and Cgs, respectively.
As is known, for a parallel plate type capacitor configuration (which the gate-to-source and gate-to-drain capacitances approximate), the capacitance C is a function of the dielectric (∈), the cross sectional area (A) of the parallel plates, and the distance (d) between the plates; C=∈A/d). Therefore, as can be seen in prior art FIG. 3c, an excessive overlap of the gate and the drain/source (Dgd) negatively contributes to an increase in Cgd and Cgs.
One way in which designers have attempted to decrease Cgd and Cgs is to form a poly oxide layer over the gate poly, as illustrated in prior art FIG. 4a and designated at reference numeral 50. That is, after the poly gate 22 has been defined, an oxide 52 is grown around the poly, thereby forming an oxide sidewall 54 on the lateral edges of the poly, having a particular thickness (t). Using the poly oxide 52, a subsequent implantation of dopants 40 is spaced laterally away from the gate by a distance (txe2x80x2) which approximates the poly oxide thickness (t). Consequently, any subsequent anneal results in a lesser amount of source/drain under the gate electrode and thus less gate overlap capacitance. Unfortunately, forming poly oxides 52 having thicknesses greater than about 50 Angstroms results in more silicon being consumed which leads to a silicon recess and increased series resistance, which disadvantageously lowers drive current. In addition, as illustrated in prior art FIG. 4b, the implantation dopants 58 are attracted to the poly oxide sidewall 54, resulting in a poorly controlled dopant loss in the substrate (sometimes referred to as segregation). Due to the segregation and the poor flexibility in fashioning the poly oxide thickness, the poly oxide solution has not served reliably to satisfactorily reduce Cgd and Cgs, respectively.
Another solution employed to reduce the Cgd and Cgd of transistors is to alter the shape of the gate electrode, for example, by generating a T-shaped gate electrode structure, as illustrated in prior art FIG. 5a and designated at reference numeral 60. As illustrated in FIG. 5a, the T-shaped gate electrode 60 has a top region 62 which is larger than a bottom region 64 which interfaces with the gate oxide 24. Consequently, a xe2x80x9cgate footprintxe2x80x9d 66 which shields the underlying substrate during a self-aligned source/drain implantation is dictated by the larger, top region 62 of the gate electrode 60. As illustrated in prior art FIG. 5a, this spatial relationship causes the implantation dopants 40 to be spaced further away from the smaller, bottom gate portion 64. Consequently, during subsequent thermal processing, the lateral diffusion of the drain and source regions 14 and 18 results in a lesser amount of overlap 68 (Dgd) with respect to the gate electrode, as illustrated in prior art FIGS. 5b-5c, respectively. With a reduction in the overlap (Dgd or Dgs) between the gate and the source, and the gate and the drain, respectively, the cross sectional area (A) associated with the parallel plate capacitor model is reduced substantially.
Although the T-shaped gate electrode configuration of FIGS. 5a-5c provides for a favorable reduction in Cgd and Cgs, fabricating devices using such a T-shaped gate electrode has proved challenging. For example, one prior art method of fabricating a T-shaped gate electrode employs a multi-step etch process, for example, as illustrated in prior art FIGS. 6a-6b, and designated at reference numeral 70. Looking to FIG. 6a, a polysilicon layer 72 is etched using a first etch chemistry to generate a generally anisotropic etch profile 74 for a predetermined period of time. Subsequently, as illustrated in prior art FIG. 6b, a second etch chemistry is employed which is generally isotropic, thereby causing an xe2x80x9cundercutxe2x80x9d in a bottom portion 76 of the polysilicon 72 which causes the feature of interest to have a notch 78 which approximates a T-shape feature when performed symmetrically.
The prior art etch solutions are not desirable because they tacitly utilize the polymer formation on the sides of the gate. The polymer is formed from the deposition of etch products and resist, and the polymer is thicker on the top of the gate than on the bottom thereof. The prior art methods exploit the etch rate difference between the polymer and the polysilicon. However, the process control of the notch depth and height is difficult. Such difficulty is caused by the various etch steps having different polymer formation rates, the polymer type perhaps being different in different steps, and the polymer etch rate not being well known.
Since a T-shaped gate electrode structure provides substantial advantages in reducing the Cgd and Cgs of transistor structures and thus advantageously improves transistor speed, there is a need for a method of forming the T-shaped gate electrode structure in an easy and controllable manner.
The present invention relates generally to a method of forming a generally T-shaped silicon structure, for example, for use as a gate electrode to thereby reduce a transistor capacitance associated therewith.
The present invention relates to a method of forming a generally T-shaped silicon structure. The invention comprises using a layered stack of differing silicon materials and exploiting a variation in the etch characteristics associated therewith to generate the generally T-shaped structure in a controllable fashion. Use of such a structure in a semiconductor manufacturing process allows for the formation of T-shaped silicon structures as gate electrodes.
According to one aspect of the present invention, a method of forming a generally T-shaped silicon structure comprises forming a poly/amorphous silicon layer stack, wherein a polysilicon layer underlies a generally amorphous silicon layer. The method further comprises etching the poly/amorphous silicon layer stack in multiple steps, for example, the BARC (bottom anti-reflective coating) step, the breakthrough (BT) etch step, the main etch (ME) step, the endpoint (EP) etch step, and the over etch (OE) step. The OE step may be the last step in the multi-step process, and is generally used when most of the polysilicon has already been removed from the wafer. The OE is used primarily to ensure that no polysilicon remains on the wafer except under mask covered areas. Some of these etch steps may have identical or very similar process conditions.
Since the generally amorphous silicon layer on top of the stack etches at a slower rate than the underlying polysilicon layer during the over etch step, an amount of lateral etching in the generally amorphous silicon layer is less than the underlying polysilicon. Consequently, a lateral portion of the generally amorphous silicon layer extends beyond a corresponding lateral portion of the underlying polysilicon layer, thereby resulting in a generally T-shaped silicon structure.
According to another aspect of the present invention, the formation of a poly/amorphous silicon layer stack comprises depositing via chemical vapor deposition (CVD) a silicon material in a CVD chamber at a first temperature (e.g., about 595xc2x0 C. or more) to form a polysilicon layer. The method further comprises altering a chamber temperature and depositing via CVD a silicon material in the CVD chamber at a second temperature (e.g., less than about 595xc2x0 C.) to form a generally amorphous silicon layer over the polysilicon layer. In the above manner, the poly/amorphous silicon layer stack is formed in a single processing chamber, thereby allowing the layer stack to be formed with minimal contamination. In addition, by varying a temperature associated with the deposition of the generally amorphous silicon layer, an amount of amorphorization may be controlled, thereby resulting in controllable variations in the etch rate thereof, as may be desired. Further still, by varying a time by which the polysilicon layer and the generally amorphous silicon layer are deposited, the thicknesses may be varied and such thickness variations may be employed to vary an aspect ratio associated with the resulting generally T-shaped structure.
According to still another aspect of the present invention, the poly/amorphous silicon layer stack is formed by forming a polysilicon layer and subsequently implanting a top portion thereof. The implantation of the top portion of the polysilicon layer causes an amorphorization of the top portion. By controlling an energy, dopant and or dose of the implantation, a thickness of the amorphous top portion may be controlled, as well as an amount of amorphorization and etch rate difference between the amorphous layer and the polysilicon layers, as may be desired.
According to yet another aspect of the present invention, a method of forming a transistor having a generally T-shaped gate electrode is disclosed. The method comprises forming a poly/amorphous silicon layer stack and etching the stack to form a generally T-shaped gate electrode. The gate electrode is subsequently utilized to self-align the source/drain regions in a subsequent implantation step. The T-shaped gate electrode causes the source/drain dopants to be spaced away from the bottom, polysilicon portion of the gate electrode such that lateral diffusion due to a subsequent anneal reduces an overlap between the gate and source, and the gate and drain, respectively. The overlap reduction reduces the gate-to-source and the gate-to-drain capacitance of the transistor, thereby resulting in an improvement in transistor speed.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.